1. Field of the Invention
This invention is related to the field of integrated circuit development methodologies and, more particularly, to static timing analysis.
2. Description of the Related Art
Static timing analysis tools are generally used in integrated circuit development methodologies to estimate the timing characteristics of a circuit being developed. The maximum frequency of operation of the circuit may be estimated by assuming “worst case” delays in the circuit elements (that is, the longest delays expected to be experienced in the fabricated integrated circuit, accounting for such factors as process variation, temperature variation, supply voltage variation, etc.). Additionally, proper operation for setup and hold times for clocked storage devices or circuit input/output signals may be estimated using “best case” assumptions for delays in the circuit elements (that is, the shortest delays expected to be experienced, accounting for the above factors).
Typically, static timing analysis tools model the delay due to the wires between circuit elements (the “interconnect delay”) as a network of resistors and capacitors. The resistors corresponding to a particular wire have resistances derived from the resistance per unit length of that wire. The capacitors have capacitances derived from the physical characteristics of the wire and nearby wires. That is, wires running along side each other (separated by an insulator) form parallel plate capacitors with a capacitance related to the surface area of the wires. Typically, a resistor-capacitor (RC) extraction is performed to extract the resistance(s) and capacitance(s) for each wire from a layout database for the circuit including the wire. The resistances and capacitances are combined to produce a delay for the wire, and the transition time on the wire (from high to low or low to high) may also be calculated from the RC extraction and the transition time at the circuit that drives the wire.
Unfortunately, the static RC data for a wire may not accurately reflect the delays experienced on that wire. For example, one effect that is not accounted for is the Miller effect. The Miller effect states that the effective capacitance between the terminals of a capacitor is dynamic and is based on the switching state of the terminals. If only one terminal is switching, the effective capacitance may be a first value. If both terminals are switching simultaneously in opposite directions at the same rate, the effective capacitance is twice the first value. If the terminals do not switch simultaneously, or at the same rate, the effective capacitance is greater than the first value but less than twice the first value. If both terminals switch simultaneously in the same direction at the same rate, the effective capacitance may be zero. If the terminals do not switch simultaneously, or at the same rate, but do switch in the same direction, the effective capacitance is greater than zero but less than the first value.
Thus, the delay on a given wire may be a dynamic value based on the switching state of nearby wires, and may vary substantially from the delay calculated using the RC extraction values. Some timing analysis tools attempt to account for Miller effect using “timing windows”. That is, a window of time around the switching on a given wire is defined, and the tool determines if other wires are switching during the timing window. This approach may help account for Miller effect, but may be complex and time consuming. Furthermore, for high frequency integrated circuit designs, the timing windows may overlap substantially, further complicating the analysis. Another attempt to model Miller effect may be to assume a “rule of thumb” for Miller effect and modify all capacitances for all wires in the integrated circuit by the same rule of thumb. Such a rule of thumb approach may not provide a very accurate Miller effect accounting for a given wire.